# Oriv

An environment for embedded engineers that catches errors before the design is finalized.

Oriv Studio showcases engineering design in multiple perspectives. The ability to show interaction of multiple components under thermal, power, interface, tolerance, emission, etc. perspectives is unique to Oriv. The knowledge layer developed within the tool provides the ability to test interaction of design elements and reduce risk much earlier than traditional design approaches currently in place.

## Real-time reasoning,  when the design lives in the knowledge model.

The entire design including requirements, specifications, datasheets and the historical decisions made are part of your knowledge model. Oriv Studio helps log, trace and simulate during ideation phase of a product, much before hardware or specifications are even considered. The ability to recompute drives the ability to avoid risk and drifts away from design goals enabling and capturing all organizational capabilities over time.

## Connects to tools engineers already use.

Oriv Studio is where engineers design. The knowledge layer is the record Studio keeps of why they designed it that way. Every tool in the stack can read it over REST, GraphQL, SQL, or MCP. Oriv doesn't replace the EDA, PLM, test bench, simulation, or AI tools the team already trusts. Those tools own the schematic, the BOM, and the test result. What Oriv does replace is the vendor calculator opened once per part, and the spreadsheet kept beside it.

## Eight perspectives on the same system model. Each one reveals a different class of risk.

Oriv Studio keeps the entire design in a single knowledge model for the organization to utilize, making perspectives available as needed to engineers and their teams. It also provides the ability to recalculate and recompute based on change requests, flag any anomalies outside of model thresholds.

All of this available in Oriv Studio, or over REST and MCP.

- **Power budget**: The rail budget keeps up with the design. 1.4 W on a 1.6 W regulator, flagged at 88 %.
- **Thermal**: Oriv has the junction temperature before the board exists. Power passes at 1.42 W. Junction fails at 108 °C. Same run.
- **Interfaces**: A connection has two datasheets. Oriv checks them against each other. 6 connections checked. 1 level mismatch, found on the diagram.
- **Tolerances**: Oriv calculates worst-case corner cases. 3V3 lands at 3.42 V hot. Spec stops at 3.40 V. Flagged.
- **Emissions**: Oriv shows the net behind every peak before the chamber does. Two peaks, each traced to one datasheet parameter.
- **Lifecycle**: Two parts can match on paper and behave differently. Four behaviours per candidate. One gap flagged.
- **Test bench**: Oriv Studio creates the bench configuration for SuT, I/O and simulation together. RIG-02 derived from RIG-01. 14 requirements linked.
- **Panel builder**: A written instruction builds the panel. 5 widgets. 5 bindings resolved. 0 wired by hand.